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SPT7851
10-BIT, 20 MSPS, 79 mW A/D CONVERTER
FEATURES
* * * * * * * * 10-Bit, 20 MSPS Analog-to-Digital Converter Monolithic CMOS Internal Track-and-Hold Low Input Capacitance: 1.4 pF Low Power Dissipation: 79 mW 2.8 - 3.6 V Power Supply Range TTL-Compatible Outputs -40 C to +85 C Operation
APPLICATIONS
* * * * * * * CCD Imaging Cameras and Sensors Medical Imaging RF Communications Document and Film Scanners Electro-Optics Transient Signal Analysis Handheld Equipment
GENERAL DESCRIPTION
The SPT7851 10-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS process. It delivers high performance with a typical power dissipation of only 79 mW. With low distortion and high dynamic
range, this device offers the performance needed for imaging, multimedia, telecommunications and instrumentation applications. The SPT7851 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (-40 C to +85 C).
BLOCK DIAGRAM
ADC
DAC
+ - G=2
D<1...0> Pipeline Stage
VIN+ VIN- VREF+ VREF- CLK Clock Driver Digital Delays, Error Correction and Output 10 Stage 1 Stage 2 Stage 9 Stage 10
Digital Output (D0 - D9)
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VDD1 .............................................................................. -0.5 V to +6 V VDD2 .............................................................................. -0.5 V to +6 V VDD3 .............................................................................. -0.5 V to +6 V Input Voltages Analog Input ................................. Digital Input .................................. VREF+ ........................................... VREF- ........................................... CLK .............................................. Note: -0.5 V to (VDD +0.5 V) -0.5 V to (VDD +0.5 V) -0.5 V to (VDD +0.5 V) -0.5 V to (VDD +0.5 V) -0.5 V to (VDD +0.5 V) Temperature Operating Temperature ............................. -40 to +85 C Storage Temperature ............................... -65 to +125 C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN-TMAX , VDD1 = VDD2 = VDD3 = 3.3 V, VREF- = 1.0 V, VREF+ = 2.0 V, Common Mode Voltage = 1.65 V, CLK = 20 MSPS, Bias 1 = 90 A, Bias 2 = 9.5 A, Differential Input, Duty Cycle = 50%, unless otherwise specified. PARAMETERS DC Accuracy Resolution Differential Linearity Integral Linearity No Missing Codes Analog Input Input Voltage Range (Differential) Common Mode Input Voltage Input Capacitance Input Bandwidth (Large Signal) Offset (Mid-scale) Gain Error Reference Voltages Reference Input Voltage Range (VREF+ - VREF-) Negative Reference Voltage (VREF-) Positive Reference Voltage (VREF+) Common Mode Output Voltage (VCM) VREF+ Current VREF- Current Switching Performance Maximum Conversion Rate Pipeline Delay (See Timing Diagram) Aperture Delay Time (TAP) Aperture Jitter Time TEST CONDITIONS TEST LEVEL MIN SPT7851 TYP 10 0.6 0.75 Guaranteed 0.6 1.2 1.0 1.65 1.4 120 1.0 0.3 1.0 1.0 2.0 1.65 35 -25 1.7 1.9 MAX UNITS Bits LSB LSB
V V VI IV IV V V V V IV IV IV VI V V VI IV V V
VIN+ = VIN- = VCM
V V pF MHz % FSR % FSR V V V V A A MHz Clocks ns ps-rms
0.6 0.9 1.9 1.3
1.7 1.3 2.9 1.8
IO = -1 A
20 7.5 5 10
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ELECTRICAL SPECIFICATIONS
TA = TMIN-TMAX , VDD1 = VDD2 = VDD3 = 3.3 V, VREF- = 1.0 V, VREF+ = 2.0 V, Common Mode Voltage = 1.65 V, CLK = 20 MSPS, Bias 1 = 90 A, Bias 2 = 9.5 A, Differential Input, Duty Cycle = 50%, unless otherwise specified. PARAMETERS Dynamic Performance Effective Number of Bits IN = 5.0 MHz IN = 10.0 MHz Signal-To-Noise Ratio IN = 5.0 MHz IN = 10.0 MHz Total Harmonic Distortion IN=5.0 MHz IN=10.0 MHz Signal-To-Noise and Distortion IN = 5 MHz IN = 10 MHz Spurious Free Dynamic Range IN = 5.0 MHz IN = 10.0 MHz Differential Phase Differential Gain Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Power Supply Requirements Supply Voltages VDD1, VDD2, VDD3 Supply Current IDD Power Dissipation Power Supply Rejection Ratio (PSRR) TEST CONDITIONS TEST LEVEL MIN SPT7851 TYP MAX UNITS
VI V VI V VI V VI V VI V V V VI VI VI VI V VI VI IV
9.0
9.3 9.0 58 58 -68 -60 -61
Bits Bits dB dB dB dB dB dB dB dB Degrees %
57
56
58 56 70 61 0.2 0.5
62
80% VDD 20% VDD 1 1 1.8 85% VDD 4 95% VDD 0.1 8 A A pF V V ns
VIN = GND VIN = VDD
IO = -2 mA IO = +2 mA
0.4 12
IV VI VI V
2.8
3.3 24 79 67
3.6 30 100
V mA mW dB
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL TEST PROCEDURE I II III IV V VI 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
80
THD, SNR, SINAD vs Sample Rate
80
THD, SNR, SINAD (dB)
70
70 THD 60 SNR SINAD 50 THD SNR SINAD
THD, SNR, SINAD (dB)
60
THD SNR SINAD
50
40
40
30
30
20 100 101 102
20 10 0 101 102
Input Frequency (MHz)
Sample Rate (MSPS)
Note: Bias1 and Bias2 currents optimized for each sample rate.
THD, SNR, SINAD vs Temperature
70
150
Power Dissipation vs Sample Rate
68
THD, SNR, SINAD (dB)
THD
66
Power Dissipation (mW)
125
100
64
75
62
50
60
SNR
58
25
SINAD
56 -40 -25 0 25 50 70 85
0 10 0 101 102
Temperature (C)
Sample Rate (MSPS)
Note: Bias1 and Bias2 optimized for each sample rate.
Bias 1 Voltage vs Bias 1 Current
3.4 3.2 0.85 3.0 0.90
Bias 2 Voltage vs Bias 2 Current
VBias 2 (V)
VBias1 (V)
0.80
2.8 2.6 2.4 2.2 2.0 0 30 60 90 120 150 180
Bias 1 30 60 90 120 150
VBias 1 2.19 2.53 2.79 3 3.22
0.75 0.70 0.65 0.60 0 3 6 9
IBias 2 3 6 9 12 15
VBias 2 0.6975 0.7535 0.796 0.8295 0.8595
12
15
18
IBias1 (A)
IBias 2 (A)
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Figure 1 - Timing Diagram
Sampling Points N-1 N N+1
tAP AIN CLK
N+2
N+6
N+7
N+8
tD DOUT
N-2 N-1 N
GENERAL DESCRIPTION
The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC. It has a pipelined architecture and incorporates digital error correction of all 10 bits. This error correction ensures good linearity performance for input frequencies up to Nyquist. The inputs are fully differential, making the device insensitive to system-level noise. This device can also be used in a single-ended mode. (See analog input section.) With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications in the range of 1 to 20 MSPS. Figure 2 - Typical Interface Circuit
TYPICAL INTERFACE CIRCUIT
The SPT7851 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7851 in normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to consider for achieving the optimal device performance.
+3.3 V
4.7 F + .01 F 10 F +
CLK In
(3 V Logic)
Ref- In
(+1.15 V)
+3.3 V
.01 F
Ref+ In
(+2.15 V) + 4.7 F .01 F 11
+3.3 V Digital
0.1 F 1
GND CLK N/C
Decoupling Cap
VDD2
VDD3
VDD1
VRef-
VRef+
VDD1
VDD2
VDD1
12
N/C N/C N/C
VDD3 44 DNC DNC D0 D1 (LSB)
90 A 9.5 A .01 F (+1.65 V)
GND Bias1 Bias2 VCM GND
U1 SPT7851
D2 D3 D4 D5 D6 D7 D9 D8
Interfacing 3 V Logic
RF In
51
68 pF
VIN+ VIN-
22 Minicircuit T1-6T
GND
GND
34
(MSB)
23
33
AGND
FB
DGND
Note: 1. All VDD1, VDD2 and VDD3 should be tied together. 2. FB = Ferrite Bead; must be placed as close to U1 as possible.
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ANALOG INPUT
The input of the SPT7851 can be configured in various ways depending on if a single-ended or differential, AC- or DCcoupled input is desired. The AC coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the VCM pin as shown in figure 2. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the inputs attenuates kickback noise from the internal sample and hold. Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a a DC-coupled single-ended input is desired. The selection criteria of the buffer op-amps is as follows: Open loop gain >75 dB Gain bandwidth product >50 MHz Total Harmonic Distortion -75 dB Signal-to-Noise Ratio >75 dB
REFERENCES
The SPT7851 has a differential analog input. The voltages applied to the VREF+ and VREF- pins determine the input voltage range and are equal to (VREF+ - VREF-). This voltage range will be symmetrical about the common mode voltage. Externally generated reference voltages must be connected to these pins. (See figure 2, Typical Interface Circuit.) For best performance, these voltages should be symmetrical about the midpoint of the supply voltage.
COMMON MODE VOLTAGE REFERENCE CIRCUIT
The SPT7851 has an on-board common mode voltage reference circuit (VCM). It is typically one-half of the supply voltage and can drive loads of up to 20 A. This circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit.
BIAS CURRENT CIRCUITS
The bias currents suggested (Bias 1 and Bias 2 in figure 2) optimize device performance for the stated sample rate of 20 MSPS. To achieve the best dynamic performance when operating the device at sample rates other than 20 MSPS, the bias current levels should be adjusted. Table I shows the settings for Bias 1 and Bias 2 for selected sample rates. The "Bias Voltage vs Bias Current" graphs on page 4 show the relationship between the bias current and the bias voltage. Please refer to the application note for more information. Table I - Sample Rate Settings
Figure 3 - DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown)
R3 VCM (R3)/2 - + Input Voltage (0.5 V) R2 R2 R - + 15 pF VIN- 51 R R 51 VIN+ R3 R ADC
+ - R
51
Sample Rate (MHz) 1 5 10
Bias 1 (A) 30 50 70 90
Bias 2 (A) 3.0 6.0 7.5 9.5
POWER SUPPLIES AND GROUNDING
The SPT7851 is operated from a single power supply in the range of 2.8 to 3.6 volts. Nominal operation is suggested to be 3.3 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible.
20
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CLOCK
The SPT7851 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non50% duty cycle reduces the settling time available for every other stage and thus could potentially cause a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2 ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed.
input results in an all 1's code (111...1). The output data is available 7.5 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up.
EVALUATION BOARD
The EB7851 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7851. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7851) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability.
DIGITAL OUTPUTS
The digital output data appears in an offset binary code at 3.3 V CMOS logic levels. A negative full scale input results in an all zeros output code (000...0). A positive full scale
PACKAGE OUTLINE
44L TQFP
A B
INCHES SYMBOL A B MIN 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.039 Typ 0-7 0.018 0.057 0.006 0.030 MAX
MILLIMETERS MIN 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.300 1.35 0.05 0.450 1.00 Typ 0-7 0.45 1.45 0.15 0.750 MAX
Pin 1 Index
C D E F
C D
G H I J K
E
F
G I H J K
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